The present invention relates to a semiconductor technology, and more particularly to a ferroelectric capacitor having a vertical structure.
In recent years, a nonvolatile ferroelectric memory cell and a ferroelectric random access memory (FRAM) having the foregoing memory cell array comprising, as an interelectrode insulation film of a capacitor for storing information, a ferroelectric thin film made of a material having a perovskite structure have attracted attention.
The ferroelectric film has a characteristic such that electric polarization generated once when an electric field has been applied is retained even if the electric field is removed and the direction of the polarization is inverted when an electric field having intensity exceeding a certain level is applied into a direction opposite to the direction of the foregoing electric field. Taking notice of the characteristic of the dielectric material for inverting the direction of polarization, a technique has been developed to form a FRAM cell by employing a ferroelectric material to form an insulation film of an information storing capacitor of a memory cell.
The FRAM cell has a structure in which a ferroelectric capacitor is substituted for a capacitor of a DRAM cell. The FRAM employs a method in which a charge in a polarization switched or non-switched state is fetched from a ferroelectric capacitor through a switching MOS transistor. Thus, the FRAM has a characteristic that data xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d written and stored on a memory cell is not lost even if the operating power source is turned off. The FRAM has such a characteristic so that FRAM does not require a refreshing operation to store data and no electric power is required in a standby mode, as compared with the conventional Flash memory. Moreover, operation voltage for FRAM is about 5V much lower than the voltage of about 18V for the Flash memory, and power consume is reduced.
The FRAM cell includes a transistor-a capacitor (abbreviated to 1T/1C) structure composed of one transistor and one ferroelectric capacitor generally with a stacked structure. Referring to FIG. 1, a MOS transistor including a gate electrode 12, gate dielectric layer 14 and source/drain regions 16 is formed on a semiconductor substrate 10. An insulating layer 20 formed over the semiconductor substrate 10 has a contact plug 22 coupled to one of the source/drain regions 16. A horizontal stacked ferroelectric capacitor is formed on the contact plug 22. The conventional ferroelectric capacitor is formed in a way of horizontal stacking in a sequence from bottom to top. A lower electrode 24 is formed on the contact plug 22, and a ferroelectric film 26 and an upper electrode 28 is formed in sequence on the lower electrode 24. Substantially enough plate area is required for keeping capacitance of ferroelectric capacitor to prevent data loosing. As increasing integration of FRAM, the usage area of the FRAM cell is relatively decreased, and the fabricating area for ferroelectric capacitor is correspondingly decreased thereby resulting in a capacitance deficiency.
In addition, a horizontal ferroelectric capacitor is generally formed by utilizing deposited stack layer, and then defines the shape of the capacitor by lithographic and etching technology. However, during depositing conductive material for forming lower electrode, grain effect will be appeared in top portion of lower electrode and thus reducing electric conductivity. Furthermore, the edge of the ferroelectric capacitor will be damaged during the etching process, and thus a local leakage problem results.
The present invention provides a vertical ferroelectric capacitor structure and the method of fabricating the same, which can reduce the area for capacitor, increase the memory capacity of ferroelectric memory, and decrease grain effect and etching effect during fabricating process.
The present invention provides a ferroelectric capacitor structure adapted for a semiconductor substrate. The ferroelectric capacitor structure comprises two vertical plate electrodes and a ferroelectric layer between the two vertical plate electrodes. Wherein, the height of the vertical plate electrodes is larger than the thickness of the vertical plate electrodes, and the height of the vertical plate electrodes is also larger than the thickness of the ferroelectric layer.
The present invention also provides a method of fabricating a vertical ferroelectric capacitor. A semiconductor substrate is provided. An insulating layer having a first opening and a second opening is formed on the semiconductor substrate. The first and second openings are then filled with a conductive material to form a lower electrode and an upper electrode. A portion of the insulating layer is removed by lithographic and etching technology to form a gap between the lower and upper electrodes. The gap between the lower and upper electrodes is then filled with a ferroelectric material.
Since the lower and upper plate electrodes are in a vertical and a parallel arrangement, the area of the ferroelectric capacitor can be properly reduced by increasing the height of the ferroelectric capacitor. Accordingly, the amount of memory cells in the ferroelectric memory can be improved and thus increase the memory capacity. Moreover, the etching damage in the fabricating process also can be reduced.